You plus if you happen to consider we’re talking concerning the various design for testability techniques which make lifestyles less complicated for the experiment engineers in phrases of the hassle they ought to put in for testing now within the structure DFT systems that we now have pointed out we talked about procedures like scan chain and partial chain which can be very wellknown methods which might be followed in the enterprise whereby given a design we add scan gels to it with the net outcomes is that the ensuing circuit anything we get is far less complicated to scan ok there is an extra general philosophy which is also invites produce that’s referred to as constructed in self-experiment well here we are trying to add some more circuitry throughout the chip in order that the chip can scan itself however there are a quantity of disorders that must addressed right here so in the lecture at present we will try to handle a few of these problems which are posed with the aid of the excellent built in self-scan strategies which are used so first allow us to attempt to see what is that this built in self-scan method and what does these involve well built in self-test is valuable for discipline test and prognosis field test means in the special environment where you are using the chip in terms of the appliance that you may experiment the chip there itself in contrast if you’re utilising design for testability approaches then the chips ought to be verified in a targeted laboratory where you might have an automatic scan apparatus hooked up and in view that this ates are very expensive equipments so having high-quality and utilising it for trying out is normally so much less pricey now speakme about subject scan and prognosis so earlier many used some kind of software exams or Diagnostics to scan the modules are the subsystems which might be working appropriately or which can be failed but the concern with program tests is that the hardware fault coverage will not be that high and additionally on account that these are application packages which can be going for walks they’re relatively slow to function so a better approach is to have some unique hardware mechanism utilising some unique reason hardware we will have this constructed in self-experiment mechanism so you probably have this the process assessments effort shall be so much lowered when you consider that already there’s some hardware inside the chip a good way to care for just about the whole lot since of this the system upkeep and restore routine will likely be a lot better and you can have higher prognosis because the aspect stage for the reason that if a element fails the element itself will announce that good i am bad good enough so now let us see that what are the principal experiment issues that a tackle door manage in base strategies which otherwise would pose a massive drawback to the scan engineers ok so the most important experiment challenge that I multiplied by way of high-quality are as follows well that the quantity of accessories in a chip are growing daily but the quantity of pins of the chip is just not increasing in the equal proportion so growing chip good judgment to pin ratio is a predominant predicament which means that the controllability and observability of the common sense throughout the chip goes down daily so when you’ve got some special motive hardware throughout the chip to scan the common sense within so it is going to be a lot useful well this can be a related factor more and more dense instruments and of course faster clocks this is one essential issue nowadays we run the circuits at much higher clock frequencies however in approaches like design for testability DFT scan path there we rather do not test this circuit at its full velocity or full frequency because we need to scan in the data within the scan chains after which simplest we are able to follow a scan vector and we can see the output so the frequency at which we are genuinely working the working the circuit is way minimize than the exact supposed running frequency however in bist we will do the testing on the actual first clock price and the increasing experiment new release and experiment application instances that may also be increased with the aid of bist considering that it is finished robotically within and considering the fact that we’re utilising computerized scan equipments and the scale of the scan vectors required is increasing day by day so the reminiscence requirement of a TS is also growing so these problems are additionally addressed and in T’s which work at 1 gigahertz clocks are bigger are very pricey this is one problem and steadiness insertion with appreciate to DFT is just not perpetually very effortless in view that designers typically designer work on the behavioral level so the CAD tools routinely will translate the behavioral stage into gate stage so once we speak about inserting some testability which you could say elements on the gate degree implementation design so it becomes a problem good enough so designer might not be very much accustomed to the gate degree good judgment with the synthesizer has synthesized in view that after optimization traditionally it is very problematic to identify the gate level common sense accessories and correlate it with the greater level habits degree components ok so these are the problems and now let us try to see that what are the special accessories of charges which can be worried in having a bist implementation adequate so the primary and apparent fee is naturally the affordable field overhead for the further hardware that you just need well good if we wish to do the testing throughout the chip we’d like two matters we need a hardware sample generator inside the chip and we’d like some sort of a hardware response compactor or response calculator within the chip and there must be a designated purpose controller so that it will be controlling these two so these are the three additional extra Hardware blocks that we want throughout the chip and for these we’d like these further chip subject over it is no longer best that we need further pins we must have as a minimum one extra pin that will tell the chip that well now I wish to scan to prompt the satisfactory operation there can be one pin zero means common operation and one approach great mode adequate and due to the fact we are including all this further hardware add-ons there can be efficiency over it penalties additionally due to the fact that some further path delays will get inserted because of these fine hardware that now we have inserted and prior we had mentioned that if we broaden the chip discipline the chip yield may even drop now when you consider that we’re adding some extra add-ons chip subject goes up so yield may also go down so these are the different add-ons of the price involved in waste chip subject over it pin we’d like one further pin a bit of bit of performance over it and of direction related Eid loss well of path in latest multi-million gadget chips this yield and chip array overhead aren’t that fundamental in view that the broaden will likely be particularly marginal okay now just looking at the total bist architecture let us try to see what are the exceptional due to the fact that the main Hardware blocks that we need to prompt the pleasant and to work just utilizing this well now in this diagram for those who look at so the circuit that we need to test is living right here on the core that is the circuit underneath experiment these are the natural major inputs and these are the common predominant output so that is the usual path of circuit operation so most commonly this multiplexer will probably be identifying this course and this direction will get chosen now you can see that even within the average mode this multiplexer is coming as an additional prolong within the path so the prolong of the total circuit operation will get slowed down a little bit bit now in the test mode the scan controller will likely be controlling a few matters first is that there can be a hardware sample generator to be able to now be opening to generate some patterns on the way to be applied to the circuit underneath scan now the controller will even be controlling the multiplexer so that now these patterns and not this pis will come to the input of the cutsy OD now when you consider that we try to evaluate the response also within the chip so it isn’t useful to retailer all of the responses character responses and examine on the grounds that the quantity of patterns can be as excessive as say manner 1 million okay so alternatively than storing 1 million outputs and evaluating them with the with the good value saved in a ROM what is most of the time achieved is that the circuit responses are compacted so after compaction we get an extraordinarily small price out here this is sometime known as a signature so so we do not evaluate the person responses as a substitute we compare only the signature with the corresponding excellent signature so one can be saved in a small room so after assessment well we can announce that the circuit is both excellent or unhealthy okay so that is the ordinary bist structure so we are going to must speak about this pattern generation and this response compaction in some detail okay however earlier than going into these allow us to first seem at one of the crucial wellknown normal-rationale Hardware blocks which persons use in bist architecture good there that you could with ease correlate the architecture with admire to this diagram in view that we want a pattern generator we want a response compactor ok now there’s a common-purpose Hardware block which has been proposed that is referred to as constructed-in logic block observer Bilbo now Bilbo in a way it’s a normal-intent logic block basic-rationale within the sense that good oftentimes it could possibly act as a sample generator oftentimes it will possibly act as response compactor routinely it may possibly act as a typical register which is a component of the circuit so rather of alternatively of investing in a entirely new hardware what we can do is that probably the most existing registers in the circuit we can enhance them with some further logic in an effort to make them programmable in this feel now we shall see later that we can have quite simple implementations of this pattern register sample generator and response compactor by means of fairly enhancing the circuit diagram of a shift register so all these things will also be accomplished very easily but let us first see the capabilities of this Bilbo constructed-in common sense block observer in order I’ve mentioned it is a programmable Hardware block well with admire to testing this has the ability to work as a test pattern generator and in addition as a response compactor now this circuit can work in 4 one-of-a-kind modes one is a common flip-flop mode it’s a parallel in parallel out register so in this mode this register can act as a usual register which is a component of the circuit on this second mode it may well act as a pattern able sample generator and within the 1/3 mode as a response compactor now each these are situated on something referred to as linear feedback shift register that we shall come to very quickly so this linear feedback shift register is a hardware constitution which can be used to generate patterns and likewise to compact responses and the fourth mode is that you can configure them as a shift register in order that if you are utilizing scan direction then you should utilize this shift register as part of the scan chain very effortlessly ok now just one thing I wish to mention right here earlier than I proceed further is that we are speaking about lfsr established sample generator or on chip pattern generator however commonly what individuals does is that the kind of patterns that are generated that are not exactly the form of patterns which might be generated through a scan generator software which we had discussed earlier but instead what is finished a special Hardware circuit is used which is able to generate very good pseudo random patterns and i had confirmed a slide earlier I showed a typical graph previous that if you feed a circuit with pseudo random patterns and if there are enough number of pseudo random patterns then the fault insurance plan may also be pretty just right of path that you would be able to ascertain this that you may verify this through simulation earlier than sincerely truly putting in and enforcing the exceptional hardware in situation before that you can use fault simulation to discover that well honestly if i take advantage of say for instance ten thousand a few random patterns then what’s the fault insurance plan should you see or in finding that the fault coverage shouldn’t be sufficient we are able to add some more patterns k so in BIST reducing the quantity of patterns just isn’t that principal as a substitute the convenience or simplicity with which that you may generate the patterns that is extra essential okay great so with the capacity of this Bilbo allow us to take a couple of examples this is a quite simple illustration believe we’ve now we have some type of a circuit where there are registers in between believe this is a register this can be a register and there may be some combinational good judgment in between we call it reduce 1 and cut 2 and they are related like this now we need to scan this Hardware now we can do it very simply very first thing is that we will configure Bilbo right into a shift register and by means of using that shift register we are able to use the the traditional shift register scan which you use for scan path for trying out them that 0 zero 1 1 0 0 1 1 sample so by way of that we can scan the Bilbo resistors then what you are able to do for trying out this reduce one we can configure Bilbo to behave as pattern generator we will configure this Bilbo to act as response compactor so now this fellow can be generating the patterns and the output will probably be reply will be shall be compacted right here so after compaction that you would be able to compare with the nice worth and notice that whether it’s excellent or bad in a similar way when you are looking to experiment circuit beneath experiment – then this Bilbo might be generating the patterns and this one shall be compressing ok so in this way in a natural circuit by using configuring probably the most registers as Bilbo registers we will make this self checking out work of direction we’d like a test controller with a purpose to be generating the manipulate indicators and the indispensable sequencing that first the first Bilbo must be producing patterns they will have to be compacting within the 2d step the second must be generating pattern and the first one must be compacting so these matters must be controlled via a separate small test controller which will have to even be throughout the chip ok well now let us take one other instance which is slightly more tricky let us take an illustration like this these are combinational blocks reduce one cut two and reduce three good these are some registers say one here one right here and one right here now when you appear at the nature of the circuit this one can be used only for producing patterns under no circumstances for compaction in a similar way this one can be used just for compaction never for producing patterns on account that that is the sink so only the core registered this one will have to be configured as a suitable Bilbo okay however the different two will have to no longer be as tricky as a whole Bilborough resistor they may be able to work exceptionally either as a sample generator or as a response compactor okay so here what you can do is that well while we’re testing say reduce one and cut two this is the trying out segment 1 then lfsr 1 can generate the experiment patterns these experiment patterns will also be fed concurrently to cut 1 and reduce 2 we will scan both of these collectively now the response of reduce one will be compacted here and the response of reduce 2 might be compacted here adequate so checking out of reduce or uncut 2 can go on collectively now after that in the trying out segment 2 what you can do Bilbo 2 may also be producing the patterns and lfsr three will also be compacting in an effort to scan this cut 3 now this approach is clearly called scan XI dueling so this is a very small example i have taken but traditionally this information course will be rather tricky and we will be able to ought to discover a agenda like this this time table for example contains two phases so there may also be many such so we’ll ought to find out a agenda so as to be taking up the entire minimum amount of time for trying out so that you can discover that in some intermediate step we will that you could clearly scan a quantity of blocks whilst a good way to have some parallelism there k first-class now speaking of the sample iteration now good we’re speaking about sample generation on chip throughout the chip so here we’ve a few alternatives first is that we can have deterministic patterns which are generated by means of a conventional scan sample generator and we are able to retailer them in a ROM but the obstacle is that the size of the ROM will likely be very huge and this can be an costly solution ok seeing that often this patterns should not have so much relationship amongst themselves and you cannot use some thing less than a ROM to store them k the 2nd alternative is that many men and women have proposed this procedure is also that you practice all possible enter combinations to the circuits beneath test because of this the experiment sample generator can be a simple counter but the quandary is that if the quantity of inputs is for illustration 30 then the number of patterns you have to follow is 2 to the vigour 30 now in a realistic circuit quantity of inputs will also be as high as 50 60 or 100 so then the quantity of patterns to be utilized will come to be astronomically excessive and it’s impractical so this is too time-ingesting now the 0.33 procedure this additionally many individuals have proposed this is some thing known as pseudo exhaustive pseudo exhaustive is some thing like this say i’ve a circuit say my circuit has three outputs there are a few inputs k recognize through inspecting the circuit structure we will find say for instance this output quantity one is elegant on best these set of inputs that is called the so-referred to as cone of influence the first for the 2nd output say for instance is elegant on these and the final output is say is stylish on the final three so the primary output is based on these inputs the 2d output is stylish on these inputs and the 1/3 output is based on these inputs now pseudo exhaustive scan pattern what it says is that you attempt to generate patterns on the enter in this sort of approach that with appreciate to those blocks this block of four this block of 5 and this block of three all of them get all viable combos among themselves for instance among the first 4 you get all sixteen combos applied good there may be some repetition but you don’t mind repute but as a minimum all potentialities perhaps they are now pseudo exhaustive says that the complete enter here is eight for instance so if we apply whole exhaustive pattern it will had been 256 however it says that you simply try to generate a number of patterns which is much less than 256 and in an effort to cover all prospects within these small subsets that is the elemental proposal in the back of this pseudo exhaustive okay high-quality and lastly now we have pseudo random patterns pseudo random patterns in fact this is most broadly used on the grounds that it’s the most effectively generated one and cost-efficient well exhaustive may readily generated but it is time but pseudo-random sample will see that it is handy to generate and it’s also fairly practical okay so now let us look at how we are able to generate pseudo random patterns making use of a linear feedback shift register okay exceptional this diagram suggests you ways a linear feedback shift register appears like say in the event you just ignore the circuit on high of this there are some D flip-flops which can be linked as a shift register so essentially it’s it is a shift register with some additional good judgment these circles are exceptional or gates well well which you could ignore these in the meanwhile count on that they are all connected ok so the outputs of the deep flip-flops they’re fed to exclusive or gates this forms some variety of a feedback community some combination of the outputs is X unusual and the XOR influence is fed again to the input of the first flip-flop now the importance of those circles is that it is not necessarily the case that the entire outputs must be exhorted so a few of these is also there say for example these three are there however this isn’t there so you selectively find out which outputs you want to exhort and also you exhort them and suggestions on the first flip-flop within the enter that is what is known as linear feedback shift register is a shift register there is a suggestions community and due to the fact that exceptional-or is a linear function we name it a linear feedback shift register now considering it’s a good defined Hardware structure so once you load it with an initial state it is going to invariably produce repeatable patterns and it has been proved by way of huge experimentation and evaluation that the that the varieties of patterns which are generated by way of this variety of an lfsr has the desirable randomness homes so that they can treat them as random patterns but a true random sample will have to no longer be repeatable on the grounds that this sample is repeatable we name it pseudo random okay pleasant now with respect to trying out if it is an n-bit register it is not the case that we ought to follow all two to the vigor n be input combos okay so the number of patterns that you simply must observe is normally much less say for instance 10,000 20,000 50,000 that must be adequate and the quantity of flip-flops will also be as excessive as 32 or sixty four but you need sufficiently lengthy sequences for excellent fault protection but how long that you just should assessment and find out by means of simulation now there are other variants of lfsr also this is one way wherein lfsr can be built and an additional style of lfsr configuration is there the place the XOR as a substitute of lying external like this they are inside this shift register like this that is known as interior XOR beasts so the place you could have this shift register with the wonderful or gates in between and the feedback path from the output you’ve got a route to the enter however probably the most amazing one you’ll must pick that which XOR gates will have got to feed k so these are the 2 special editions good now let us attempt to appear at one of the crucial mathematical homes or mathematical basis on which this lfsr headquartered I informed you which you can prefer these feedback features depending on requirement but sincerely how will we prefer that however for that let us first look at one of the mathematical homes of this linear feedback shift register the first thing we talk about is some thing called attribute polynomial this is something which is related to an lfsr so let us see that what this quite means well we start with a series of numbers let’s call them a zero a 1 km and so forth now this sequence of numbers with appreciate to an lfsr it can be treated for example if we’ve an lfsr like this so that is the output which is fed back i’m not displaying the entire diagram so this output bit this will be producing a streams of zeros and ones so this output bit pattern this can be considered because the sequence is 0 a 1 a 2 so this is a is our 0 or 1 ok now given a series of numbers like this is zero 2 am we will outline our producing function so the producing perform will also be outlined as a polynomial in some parameter variable X so this will probably be a zero plus a 1 X plus a 2 X square etc so this which you could write in closed form as m equal to 0 to infinity a M X to the power M okay now believe we’ve an N bit lfsr you could have an invidious R so let’s say these are the corresponding flip-flops 1 2 three up to n well now a 0 a 1 are the bit patterns so so on the first clock something comes out or whatever gets in is a zero it is sincerely something gets out will be fed back right here so that’s what we call a 0 so we’re assuming that the initial state that the initial state of the register is a minus 1 a minus 2 a minus 3 a minus N and feel after M clock pulses the present state looks like this a M minus 1 M minus 2 m minus 3 and M minus L and within the present state the value that is being fed again on the input out right here this shall be M so a M will probably be that linear blend of those values okay a good way to be fed again best so now if we simply look back at that diagram lfsr once more so here we had stated that the outputs of the lfsr they’re fed back by means of some blocks H h1 h2 HN now this h HS can also be 0 or 1 if it is a zero because of this that there is not any connection if it is a 1 it signifies that this is connected these are easy multipliers it multiplies with either 0 or 1 ok so either this is present or no longer gift so what i will say is that that this a a minus 1 to a minus these are the states on the present instance and centered on the linear combination of that we’re producing this am so we can write down this a.M.As follows I equal to 1 to N H I a M minus I so if I is 1 H 1 a minus 1 just wraps up H 1 is the burden and geared up with the minus 1 H 2 m minus 2 and many others good with this M now once more you go back to the expression for G X which we had computed earlier so GX we had stated is m equal to 0 to infinity a M X to the vigour M now this we can write like this as an alternative of a.M.We will substitute this I equal to 1 to n H I a minus I X to the vigour M so instead of M now we have written down this expression well now that you would be able to reorganize this a bit of bit and we can write I equal to 1 to N we can take out this H I and X i we can X out of X to the vigour M I take out X I right here so what stays is m equal to 0 to infinity a M minus I X M minus I this is what stays so this i will reorganize and write like this considering the fact that X I and this product is X to the power M find now this again the first term stays the second term if we develop this the first few terms are this and finally you get em equal to zero to infinity aim X to the power M now that is nothing however G X that is nothing however G X and this this time period this a minus half of a minus I that is nothing however the preliminary state of the lfsr okay the initial the preliminary worth which used to be loaded quality so by reorganizing the equation taking G X on this facet we can and if we just remedy it just a little bit which you could get the final expression for G X from right here G X becomes equal to I equal to 1 to n H I X I this part a minus 1 X to the minus 1 divided via 1 plus I equal to 1 to N H I X I so that is the final expression for the generating function so when you seem on the numerator the numerator is some thing there’s a part which is the preliminary state of the lfsr and of course we’ve a term this h IX I however the denominator is anything which is a polynomial of degree n so the denominator if you if you happen to develop and the denominator is customarily denoted via P X adequate so should you write down the expression for P X now from right here so P X will come to be one plus h 1 X plus H 2 X square plus 18 X to the vigour n now this polynomial px is outlined or is known as as the attribute polynomial of the lfsr now it is this characteristic polynomial which defines some homes of lfsr see if we look on the patterns which can be generated you look at the patterns which might be generated through an lfsr only one factor that you could right away notice that in the event you don’t forget the all 0 pattern good when you load the lfsr with the all 0 sample then that you could one can find that the lfsr will continually remain on this zero state it will by no means come out of it seeing that you’re feeding again by way of an XOR function and an XOR function with a set of zeros fed to the enter will give us 0 because the output so it is zero in order to again be fed back so an all zero state will depart the X will leave the lfsr indefinitely in the all zero state so after getting all zero sample within the lfsr so lfsr will stay in that state ok so this all zero sample you cannot load now there is yet another kind you could say the attribute polynomial that now we have outlined some of these characteristic polynomials are defined as primitive there’s a inspiration of primitive polynomial the notion is that the attribute polynomial px is called primitive if the periodicity of the lfsr is 2 to the vigour n minus 1 good what do mean via this now we have an N bit lfsr so an n-bit register possibly may also be in 2 to the power n viable states now out of the 2 to the vigour n viable states we have simply stated that every one zero state is dominated out once it gets into all 0 it will stay there however a primitive polynomial is one wherein if you happen to the lfsr with any nonzero state it’ll go via all 2 to the vigour n minus 1 other patterns and then it’ll come again however not like a counter it’s going to now not go through this state sequentially 1 2 3 4 5 instead it’ll go by way of in a pseudo random order that is the property of the lfsr the successive patterns might be a some randomness properties there will probably be no two patterns in order to be repeated but but you can duvet all 2 to the power n minus 1 patterns this is the very intriguing property of a primitive polynomial which you should use in the lfsr so PX is primitive if the periodicity of lfsr is creeper one so these variety of primitive polynomial may be very valuable in high-quality application very priceless seeing that consider you begin with a 32-bit lfsr but depending on virtually how many patterns you want which you can probably go up to 2 to the vigor 32 minus 1 so many patterns so you have got whole flexibility but for those who take an lfsr whose attribute polynomial will not be primitive then possibly you are going to say you will see that good good which you could generate simplest 2 to the energy say for instance 10 patterns so after each thousand 24 patterns the patterns get repeated so you particularly don’t need that you’ll desire a lfsr as a pattern generator which is able to generate beautiful huge number of patterns as you need k so lfsr that have an understanding of the primitive polynomial could be very fascinating in that sense k now if we seem at this typical textbooks for this type of linear machines lfsr you’re going to to find that the primitive polynomials of more than a few orders are listed there are ways to find out whether or not a polynomial is primitive or no longer and via exhaustive that you may say simulation and experimental stories folks have discover a list of all primitive polynomials up to very giant values of n also so i’m showing you some i’m providing you with a couple of examples these examples of primitive polynomials think in equal to 16 you’ve a sixteen stage lfsr now within the publication you are going to to find it says that the primitive polynomial is 5/3 to 0 this virtually implies that the polynomial characteristic polynomial is 2 to the energy 0 1 2 to the vigour 2 X rectangular however X three / zero X to the energy 2 X to the vigor three X cube X 5 of direction the last one will be there X 16 is implied you are taking n equal to 24 say however 24 you’re going to see that a polynomial like this is listed for 3 1 zero this means that P X is 1 plus X X dice X four X 24 say n equal to 32 28 27 1 and zero for this px is 1 plus X plus X to the vigor 27 28 plus 32 so the inspiration is that you decide on the quantity of bits of the register first how many bits you need then you definately choose a primitive polynomial after you have the polynomial you assemble an lfsr with so many flip-flops and you are taking the suggestions factor from these these are the that you would be able to say flip-flop numbers from the place you must take the suggestions and compute the XOR and suggestions so it is a relatively easy procedure so for those who construct an lfsr like this you are going to get a constitution which will generate very good pseudo random patterns as per your specifications good enough now I had acknowledged prior that whilst this lfsr acts as a just right pseudo random sample generator now solanum sample generator a pure pseudo random sample generator has a property that in each bit function the probability of zero and 1 are precisely the same so chance or the signal likelihood set is zero.5 sign likelihood is the likelihood that the road will probably be having a value of 1 now seeing that the patterns are random the possibilities of 0 and 1 are equal now in many circuits it has been determined and there are lots of you there are numerous works which are suggested in this regard there men and women say that well alternatively of pure pseudo random patterns if I apply weighted pseudo random patterns that my fault insurance plan may just strengthen so weighted pseudo random sample method good you recollect an finish gate you take a for enter and gate now with a purpose to scan a for enter and gate say for instance I wish to test the output caught at 0 fault so for checking out the output caught at 0 fault I must practice 1 in the entire 4 inputs now if the signal chance of each and every line is 0.5 i am saying that you’ve got an finish gate the sign likelihood of each and every line is zero.5 so the likelihood that the output will likely be 1 will likely be zero.5 to the vigor four this is a very small number okay which means that if we follow pure pseudo random patterns the likelihood that you’ll get a sample so they can generate a 1 within the output may be very less so for this intent very likely you’ll must generate a weighted random pattern whose input possibilities are greater than zero.5 correct ok this will also be completed very quite simply so i’ve a instructed scheme out here where in the first situation you ignore this end gates we’ve got an lfsr now we have a 8 stage LFS now this eight stage lfsr mm you realize that it generates pseudo random patterns so you are taking the output from any bit function this signal chance will be 0.5 now the interesting factor is that believe i have an end gate and that i feed the top gate with two inputs whose sign probabilities are 0.5 and nil.5 so what’s going to be sign likelihood of the output the output will be 1 if both the inputs are 1 so the probability will get elevated so the output chance will probably be 0.25 so you see that the character and say you’re taking the output of this right here the sign chance is half of you are taking an finish gate you are taking any two outputs and eight point five point 5 so output becomes zero.25 and you are taking yet another and gate but some of the inputs you feed with a probability zero.25 the other you feed with 0.5 then what’s going to be the output then 0.5 into 0.25 this will be the signal likelihood so it is going to be zero.One hundred twenty five that is 1 by way of 8 in a similar fashion 1 by way of 8 and nil.5 you put one more hand gate you’ve 1 via sixteen so so on this way that you may have sign chances 1 via 16 1 through 32 1 by way of 64 as you desire ok so this can be a multiplexer depending on this weights which you can select the multiplexer now moreover something you get for illustration you just only for the sake of discussion let’s say you get a probability of 1/4 here by way of identifying this line now we now have an XOR get in addition now if we observe this inversion enter as zero so the equal sign will likely be popping out so you can be get one-fourth probability in the output however if you practice a 1 in the inversion then this XOR gate shall be performing as an inverter so the output sign likelihood will now turn out to be 1 minus 1/4 which is three/four so by this simple stock definite that you could get so many distinctive values of the likelihood so this desk lists the entire prospects so you could have this half of 1/4 with the aid of setting the inversion to 1 that you can have 3/four in a similar fashion you can have 1/eight by way of setting in variant to 1 you could have 7 8 similarly 1/16 and 15 sixteenth so in this means well i’ve taken a very simple example with three and gates and 1 XOR gate you would develop the number of gates you should use different forms of gates so which you could generate generate a circuit which can offer you a number of special values of sign possibilities or weights now making use of that you can use that you could say you should use or you can compose a pseudo random pattern generator for the signal possibilities can also be any arbitrary price well as much as precise decision it is dependent upon if it relies on how many gates you’re utilising extra the quantity of gates higher decision you are going to get k so this weighted pattern generator in bist this has been good explored and actually even actually many men and women also advised use of this however in observe its use is just not that fashionable good so we pointed out how to generate the test patterns in a bist we had acknowledged that this lfsr is a structure which may be very widely used an lfsr has some very exciting houses it might probably generate pseudo random patterns for those who prefer if you happen to opt for a primitive polynomial then you can have 2 to the power n minus 1 so many patterns if you need them so that you would be able to excite the circuit inside the chip with the pseudo random patterns so then now now the following question is that what will we do with these circuit outputs that we get as I said we can’t personally examine each and every circuit output as it comes so first will have got to scale back them by means of some style of a compaction then only we are able to examine now in our subsequent classification we will see that how we will carry out this compaction again utilizing an extraordinarily similar structure utilizing linear suggestions shift register this we will be discussing in our subsequent classification thank you

# Lec-34 Testing Part-V

2 years ago
No Comments